Synthesizer System Description


Block Diagram


General Information

The heart of the synthesizer is a set of 2 Analog Devices AD9850 direct digital synthesis (DDS) chips. These provide 2 channels of sinewave output which may differ in frequency and relative phase. The output stage of the synthesizer also includes separate variable attenuators for the 2 channels. These attenuators have a range of 0.0 - 63.9 dB of attenuation, in 0.1 dB steps. The user therefore has control over five parameters: 2 output frequencies, 2 output attenuations, and relative phase between the 2 channels.



The DDS chips provide a 32-bit selectable frequency, and they use a reference frequency which is set at 130 MHz. Therefore, the DDS frequency resolution is 130E6 / 2^32 or 0.0327 Hz.  In this synthesizer, the user is given 0.1 Hz frequency resolution with a frequency range from DC to 35 MHz. Therefore, there are a maximum of 9 digits of frequency which may be set by the user.

The DDS DAC output spectrum includes aliased images of the output signal, the lowest frequency of which is located at Fref - Fout. A low-pass filter is needed to suppress these images; here we use a 42 MHz 5-pole elliptic filter, built from discrete components, that is specified in the AD9850 datasheet.

The output of the DDS DAC is a current ranging from 0 to a fixed ratio of the DDS programming current. In order to produce an output signal with zero DC offset, a current equal to half of the maximum DDS current must be subtracted from the node where the anti-alias filter 200 ohm impedance converts the output current into a voltage at the amplifier input.

The AD9850 provides an on-chip comparator which is used to generate a TTL sync output signal. This comparator provides a square wave output with ~50% duty cycle. A pair of AC04 inverters in parallel provide enough output drive to provide a TTL sync output into 50 ohms. The sync signals may be turned off in order to reduce system noise through a front-panel switch, which grounds the DDS chips' comparator inputs.



The signal output by the DDS and filtered by the elliptic low-pass must be amplified up to the desired +16 dBm 2 volt amplitude into 50 ohm maximum output level.  An Elantec EL2030 current-feedback operational amplifier (non-inverting configuration) provides the required gain of roughly 8.5 V/V. This op-amp was chosen for its high BW even at +10 gain, its high slew rate, and its large current drive; these features combine to allow the EL2030 to drive +/- 2 volts into 50 ohms (+16 dBm) at 35 MHz with only moderate distortion.

The distortion produced by the amplifier is present at all output levels, because the amplifier runs with a fixed gain (attenuators provide variable signal level, see below). In order to reduce the distortion levels to a respectable level (~ -50 dBc) at 35 MHz, an external 50 ohm RF low-pass filter, such as the Minicircuits SLP-50, can be hung on the channel output.  Alternatively, a TO220 footprint has been provided on the circuit board (bottom-side) that matches unity-gain buffers such as the Elantec EL2009. Such a buffer, which must run from +/- 15 V supplies, would reduce amplifier distortion (due to its high input impedance), and might itself provide less distortion into 50 ohms than the EL2030 amp. To use a buffer, the trace that jumpers the footprint's input and output pads must be cut.

See the sample spectra page for more distortion information.


Despite their hefty GBW, the Elantec amplifiers do exhibit rolloff at frequencies above 1 MHz, the rolloff reaching about 5 dB at 35 MHz.  In order to provide a constant signal level over the band of the synthesizer, the microcontroller uses interpolated lookup-table calibration settings to adjust the user-set attenuation to compensate for amplifier rolloff.  In order to implement this feature, the user must download and run the calibration software.  This software requires that the synthesizer be connected to the PC via an RS-232 serial connection.  The software prompts the user to adjust signal levels to a constant value at various frequencies.  The calibration data is then stored in the microcontroller EEPROM.  After the calibration software is run, the synthesizer will produce a constant signal level across the entire bandwidth of the device.  However, if the signal level is set at a value exceeding the maximum amplifier output at that frequency, a star (*) will be displayed indicating that the user settings have placed the channel out of proper calibration range.



The 0.0 - 63.9 dB attenuator with 0.1 dB steps actually combines three separate hardware pieces which are combined through the micro code to provide a seamless user attenuation setting. The centerpiece of the attenuation system are GaAs RF attenuators from MaCom. These are 0-31 dB 50 ohm attenuators with 1 dB steps (5 bit). A 6th bit, and therefore an additional 32 dB of attenuation, is provided by a fixed resistive attenuator that is switched into or out of the output path via a pair of complementary reed relays. With 2 relays/channel and 2 channels, 4 relays are needed.  The relays that are used in this design contain internal diodes.

The GaAs attenuator control bits tie directly to the MESFET gates in the atteunuator. Therefore, the FET control signals must assert levels beyond the maximum signal swing, which for +16 dBm is +/- 2 volts into 50 ohms. The gate control signals are generated by a level-shifting system consisting of p-channel FET arrays; the Supertex AP0332 package contains 8 pFETs with an addressable gate latch. The open drains of these FETs are tied to -8 V while the sources are tied to +5 V. The microcontroller latches attenuation bits into the FET arrays, which thus apply +5 / -8 V control signals to the GaAs control lines. Each of the 5 bits of each GaAs attenuator requires true and complementary signals. So, with 5 bits/channel * 2 FETs/bit * 2 channels = 20 FETs required, 3 Supertex AP0332 FET arrays are used. This leaves 4 free FETs, and with 4 relays in the system each requiring 1 control signal (+5/gnd), the additional FETs are used to switch the relays.

In order to provide the user with 0.1 dB attenuation resolution, the DDS programming current can be trimmed up to 10% by an EE potentiometer that is programmed by the microcontroller. Since changing the programming current to the DDS changes both the signal amplitude and the average signal level (the DDS has a current output ranging from 0 to a fixed ratio of the programming current), a second EE pot must be used to provide a dc offset cancelling current to prevent a change of DC level with the 0.1 dB steps. The 2 pots/channel * 2 channels require 4 EE pots; an Analog Devices AD8403 provides a quad EE potentiometer package, with 1k maximum resistance, 8-bit control, and a 3-wire serial interface.



The 130 MHz DDS reference clock is generated by a phase-locked loop circuit. This circuit uses a Motorola MC145170 PLL chip and Minicircuits JTOS200 VCO to convert a 10 MHz master reference into the 130 MHz DDS reference. The 10 MHz can be provided by an internal crystal oscillator or an external source as set by a switch on the back panel of the synthesizer. For an external reference, the synthesizer can either provide a 50 ohm termination or present a high impedance reference input (for chaining multiple instruments). An external 10 MHz reference should provide a signal level of at least +0 dBm.  The signal should not exceed +20 dBm or a CMOS drive level (if the input is a square wave).

The Motorola MC145170 provides on-chip R and N counters and a single-ended phase detector that provides error pulses when there is a phase difference between the two input signals. These error pulses are averaged through a low-pass filter, amplified, and passed as an error voltage to the Minicircuits VCO. This PLL is programmed in our system to operate its phase comparator at 200 kHz while providing a 130 MHz VCO output coherent with the 10 MHz reference.



The micro-code is written for the Atmel AT89S8252 8051-architecture microcontroller. It will not run on other 8051 derivates because it takes advantage of special features of the AT89S8252. In particular, the device contains 2K of EEPROM in addition to 8K of flash and 256 bytes of RAM. Another special feature of this device is the capability to be programmed in-circuit using a special serial protocol. See the Atmel AT89S8252 data sheet for more information on these special features.

The AT89S8252 includes a built-in UART which is coupled to a MAX203 RS-232 interface chip and provides a 2400 baud, 8N1, no hardware handshaking serial port. This serial port may be used by a PC to pass commands to the synthesizer, retrieve user settings, and program calibration data into the device.


There are 5 main modes of operation for the synthesizer, corresponding to the five primary parameters that may be set by the user.  The five modes are:

0 A frequency
1 B frequency
2 A amplitude
3 B amplitude
4 phase


In order to pass a command to the microcontroller, a PC must pass a byte identifying the command (command byte), a byte specifying the number of arguments that will be passed (# of args), and finally the arguments themselves. The microcontroller will execute the specified command, and will pass a confirmation back to the PC following the same byte sequence (command byte, # of args, args).

The following table lists all interface commands:


is micro alive? 0x10 0   0x10 0  
set freq, amp, or phase 0x30 2, 4, 10 1 mode byte, plus:
9 digits if freq
3 digits if amp
1 byte if phase (DDS has 5 phase bits, so 0-31)
0x30 0  
get freq, amp, or phase 0x40 1 mode of information to be returned by micro 0x40 2, 4, 10 1 mode byte, plus:
9 digits if freq
3 digits if amp
1 byte if phase
channel on/off 0x60 2 channel #, plus:
1 to turn channel on
0 to turn channel off
0x60 0  


The synthesizer board incorporates a power supply monitor / watchdog chip, the Maxim MAX813L. This chip sends a reset pulse to the microcontroller if its watchdog input detects no edges within 1.6 seconds. In addition, the chip will assert the micro reset if VCC drops below normal levels.  This function can be disabled via a jumper (see assembly instructions).



The AT89S8252 may be programmed in-circuit through a special 3-wire serial interface. Jumper J5 is the in-circuit programming header. Normally, pins 1,5,7 are jumped across to pins 2,6,8 respectively. For in-circuit programming, these jumpers must be removed. Then, use the in-circuit programmer and a PC to change the microcontroller flash.



There a total of 8 pots on the synthesizer circuit board, 4 for each channel.

R15, R35
Control the duty cycle of the sync output that is generated by the DDS on-chip comparators.

R42, R43
Control the DC offset of the output signals. They should be adjusted to eliminate any DC offset in the channel outputs.

R18, R37
Control the amplifier gain. They should be adjusted to provide an output level of 2 V amplitude for each channel.

R60, R61
Control the attenuation of the 32 dB fixed resistive attenuator that is switched by the reed relays. They should be adjusted to maintain proper attenuation as the signal level is reduced from -15.9 to -16.0 dBm.